(1) Field of the Invention
The present invention relates to a non-volatile semi-conductor memory device, and more particularly to a non-volatile semiconductor memory device capable of performing electrical write and electrical flash erasure (hereinafter referred to as "Flash EEPROM).
(2) Description of the Related Art
A typical example of the "Flash EEPROM" of the kind mentioned above is disclosed, for example, as "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory" in Journal of Solid-State Circuits, Vol. 23, No. 5, October 1988, pages 1157-1163. Performance of memories is disclosed in 1988 IEEE/IRPS, pages 158-166. Explanation on the prior art is made herein with reference to FIGS. 1-4.
FIG. 1 shows in sectional view a memory cell unit which is constituted by a drain 52 and a source 53 formed on a P-type semiconductor substrate 51, a floating gate 55 provided on a channel region between the drain and the source through a tunnel insulating film 54, and a control gate 57 provided over the floating gate 55 through an insulating film 56.
Now, performance of the above memory cell unit is explained. Data write is performed, as shown in FIG. 2, by grounding the source 53, and applying high voltages Vg and Vd to the control gate 57 and the drain 52, respectively, thereby injecting to the floating gate 55 the electrons generated by impact ionization in the neighborhood of the drain 52.
Erasure of data is performed, as shown in FIG. 3, by grounding the control gate 57, opening or grounding the drain 52, and applying a high voltage V.sub.PP to the source 53, thereby tunnel-discharging the electrons to the floating gate 55.
As shown in FIG. 4, a memory cell array is formed by having a plurality of memory cell units described above arranged in a matrix form. A plurality of word lines 58 are formed by commonly connecting the control gates of the respective memory cells positioned in the same row. A plurality of bit lines 59 are formed by commonly connecting the drains of the respective memory cells positioned in the same column. A plurality of source lines 60 are formed by commonly connecting the sources of the respective memory cells positioned in the same column.
The plurality of word lines 58 are connected to a row select circuit 62 and the plurality of bit lines 59 are connected to a column select circuit 61. The plurality of source lines 60 which are commonly connected together are electrically connected, through a switching circuit 63, to the ground (ground potential) during the reading/writing of memory cells and to an erasure control circuit 64 during the erasure of memory cells.
The non-volatile semiconductor memory device further includes a read control circuit 65 for controlling the read of memory cells and a write control circuit 66 for controlling the write of memory cells. The outputs of the read control circuit 65, the write control circuit 66 and the erasure control circuit 64 are inputted to the row select circuit 62 and the column select circuit 61.
Next, performance of the memory device is explained. During the writing, the source lines 60 are grounded through the switching circuit 63 and the control circuit 66 operates so that one memory cell is written with one bit line and one word line being caused to be made high potential by the column select circuit 61 and the row select circuit 62. During the reading, the source lines 60 are grounded as in the case of writing, and the read control circuit 65 operates so that one memory cell is read with one line and one word line being set to a predetermined voltage (about 5 V) by the column select circuit 61 and the row select circuit 62.
During the erasure of memory cells, the source lines 60 are electrically connected to the erasure control circuit 64 through the switch circuit 63, and the erasure control circuit 64 operates so that all the bit lines are turned to an open state and all the memory cells are erased with the source lines 60 being set to a high potential (about 15 V) and all the word lines being set to a ground potential.
As shown in FIG. 5, the conventional erasure control circuit is constituted by an N-channel enhancement mode transistor Q5 which has a drain electrode connected to a high voltage power supply terminal 1, a gate electrode connected to an erasure control terminal 90, and a source electrode connected to a switching circuit 63. For the erasure operation, a signal is inputted to the erasure control terminal 90 and the transistor Q5 is turned ON for an erasing time period t.sub.e during which a high voltage is applied to the source lines of the memory cells through the switching circuit 63.
The erasing time period t.sub.e is appropriately set so as not to cause the occurrence of "over-erasure". If the over-erasure occurs, the data cannot be correctly read out.
FIG. 6 shows the relationship between the threshold value V.sub.TM of the memory cell and the erasing time t. As noted from this, in the initial state, when the erasing time period prolongs (in this case, beyond T.sub.O), the threshold value of the memory cell which has been written-in in the level of V.sub.TM .about.5 V becomes a negative value. This state is a depletion state in which the transistor concerned turns ON even where the gate is grounded. This is how the over-erasure develops.
Now, it is assumed that the memory cell H in FIG. 4 is over-erased. Also, assuming that, for example, data is written in the memory cell I and the data is now to be read, then no current flows across the drain/source at the selected memory cell I.
However, since the current does flow across the drain/source at the non-selected memory cell H, the current flows also in the bit line 59 whereby the memory cell I which is an OFF bit is detected as an ON bit.
Therefore, in the conventional erasure control circuit, the erasing time period t.sub.e is so set as not to cause the occurrence of over-erase of a memory cell.
In the conventional non-volatile semiconductor memory device as described above, a problem encountered is that, due to fabrication variations, the thickness of an insulating film between the floating gate and the substrate of the memory cell (hereinafter referred to as "floating gate/substrate insulating film") tends to be too thin or too thick, in which case the over-erase or deficient erase can easily occur.
FIG. 7 is a graph showing the relationship between the threshold value of the memory cell after the erasure and the thickness of the floating gate/substrate insulating film when the conventional circuit is used. The graph shows that the threshold value of the memory cell after the erasure time of t.sub.e have the thickness dependency of the floating gate/substrate insulating film. The thinner the insulating film, the lower the threshold value after the erasure and finally the threshold value turns to a negative value, hence turning to an over-erase state.
Also, the thicker the insulating film, the higher the threshold value after the erasure, resulting in a deficient erasure. In other words, where the erasure time and the applied voltage are constant, the over-erasure or deficient erasure is caused by variations in the thickness of the floating gate/substrate insulating film.
The reason for the above is that, during the erasure, the electric field applied between the source and the floating gate is larger and the erasure speed becomes faster as the insulating film becomes thinner.
With the conventional erasure control circuit explained above, it is difficult to set an appropriate erasure time by estimating in advance the variations in the thickness of the floating gate/substrate insulating film.